1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a dynamic random access memory (DRAM) and a method of manufacturing the same which is suitable to increase integration and suppress generation of a leakage current utilizing a silicon-on-insulator (SOI) structure.
2. Discussion of Related Art
In general, a DRAM has a large memory capacity and is suitable as a semiconductor memory device for a personal computer.
A DRAM cell is profitable for high integration and has a cost per bit which is lower than that of a static random access memory (SRAM) since the DRAM cell is composed of a capacitor and a MOS (Metal-Oxide-Silicon) transistor. Thus the DRAM cell is mainly utilized as a memory device.
A memory cell region of a DRAM can utilize an N-type MOS (NMOS) which has a high carrier mobility. The memory cell region includes a capacitor formed therein. In a periphery circuit area of the DRAM, a C-type MOS (CMOS) with a low power consumption is utilized separately. The DRAM is classified as MOS memory devices, where the MOS memory devices are divided into an NMOS and a CMOS as described above.
The CMOS is divided into a bulk CMOS and a SOI (silicon-on-insulator) CMOS. In the bulk CMOS, semiconductor elements are formed on a semiconductor substrate, whereas in the SOI CMOS, a single crystalline silicon thin film is formed on an insulating layer and semiconductor elements are formed thereon.
The SOI structure in the SOI CMOS prevents latch-ups and soft errors occurring in conventional CMOS circuits since the SOI structure is not influenced by parasitic effects related to the substrate of the CMOS circuit.
The SOI technology is divided into an epitaxial growth method, a deposited film recrystallization method, and a single crystal isolation method.
In the epitaxial growth method, single crystalline silicon is grown on a single crystalline insulating layer such as sapphire. A typical epitaxial growth method is a silicon-on-sapphire (SOS) technique.
In the deposited film recrystallization method, a polycrystalline or amorphous silicon thin film is deposited on an oxide film. The deposited film is melted and recrystallized in a horizontal direction, or it is solid-phase epitaxialized (solid phase epitaxy technique).
In the deposited film recrystallization method using the melting and recrystallization technique, a polycrystalline silicon thin film is deposited on an oxide film using a CVD (chemical vapor deposition) method, and heated and melted by an energy beam such as a laser beam and an electron beam. The melted region is recrystallized on a wafer to obtain a single crystalline thin film. On the other hand, using the solid phase epitaxy technique, an amorphous silicon film is deposited on various crystalline regions of an insulating film on a substrate and is epi-grown by annealing.
In the single crystal isolation method, an insulating layer such as an oxide film is buried within a semiconductor substrate. An oxygen ion or nitrogen ion is implanted into a single crystalline silicon substrate to form a buried oxide or nitride layer while the surface of the single crystal silicon remains unchanged. This process of implanting the oxygen ion is called "Separation by IMplanted OXygen" (SIMOX).
The SOI CMOS is superior than the bulk CMOS since the SOI structure having complete isolation structure offers many merits. For example, the SOI CMOS has a low power a consumption, high integration, a high soft-error resistance, a high latch-up resistance and a high speed operation, compared to the bulk CMOS.
A conventional DRAM using SOI and a method of manufacturing the same will be described with reference to the attached drawings.
FIG. 1 is a cross-sectional view showing the structure of a conventional DRAM using SOI.
As shown in FIG. 1, the conventional DRAM using SOI includes a stack type capacitor formed on a SOI substrate which is formed by the SIMOX method. A buried oxide layer 2 is formed on a semiconductor substrate 1 and a SOI layer 3 is formed on the buried oxide film 2. Field shields 4 are formed at certain intervals on a device isolation region of the SOI layer 3. In an active region formed between the field shields 4, a first gate electrode 6a and a second gate electrode 6b are formed. First, second and third impurity diffusion regions 7a, 7b and 7c are formed in the SOI layer 3 on both sides of first and second gate electrodes 6a and 6b.
On the first impurity diffusion region 7a between the first gate electrode 6a and the field shield 4, a capacitor composed of a storage node 10, a dielectric film 11 and a plate node 12, is formed. The capacitor having the above structure is also formed on the third impurity diffusion region 7c between the second gate electrode 6b and the field shield 4. On the second impurity diffusion region 7b between the first and second gate electrodes 6a and 6b, a polysilicon pad 14 for connecting with a bitline 16 is formed over a capacitor insulating film 13. A planarizing layer 15 is formed on the capacitor insulating film 13 and polysilicon pad 14. The bit line 16 is formed on the planarizing layer 15 and connects with the polysilicon pad 14 through a contact hole formed in the planarizing layer 15. First, second and third oxide films 5, 8 and 9 formed between the above layers function as insulating layers.
FIGS. 2a to 2h are cross-sectional views for illustrating a method of manufacturing the conventional DRAM having the structure shown in FIG. 1.
As shown in FIG. 2a, using the SIMOX method an oxygen ion is implanted into the semiconductor substrate 1 in which a field region (F) and an active region (A) are defined. The implanted oxygen ion is heat-treated to form the buried oxide film 2 in the surface of the substrate 1. At this time, the semiconductor substrate 1 is a single crystalline silicon substrate. On the buried oxide film 2, a single crystalline SOI layer 3 is formed.
As shown in FIG. 2b, the field shields 4 and the first oxide film 5 are sequentially formed on the SOI layer 3 above the field regions.
As shown in FIG. 2c, polysilicon is deposited on the entire surface of the first oxide film 5 and the SOI layer 3, and selectively patterned by photolithography and etching process to form the first and second gate electrodes 6a and 6b. Then the second oxide film 8 for protecting the gate electrodes 6a and 6b is formed over of the first and second gate electrodes 6a and 6b. Impurity ions are implanted into the SOI layer 3 on both sides of the first and second gate electrodes 6a and 6b by an ion-implantation process using the first and second gate electrodes 6a and 6b as a mask. As a result, the first, second and third impurity diffusion regions 7a, 7b and 7c are formed as source/drain regions.
As shown in FIG. 2d, the third oxide film 9 is formed on the entire surface including the first and second gate electrodes 6a and 6b. Then the third oxide film 9 is selectively removed from the first and third impurity diffusion regions 7a and 7c to form node contact holes 17 above the first and third impurity diffusion regions 7a and 7c.
As shown in FIG. 2e, a polysilicon layer is formed on the entire surface of the substrate including the node contact holes 17, and selectively removed to form the storage node 10. The dielectric film 11 is formed on the surface of storage node 10. A polysilicon layer is formed on the entire surface including the dielectric film 11, and etched to form the plate node 12.
As shown in FIG. 2f, the capacitor insulting film 13 as a fourth oxide film is formed on the entire surface including the plate node 12. Portions of the capacitor insulating film 13 and third oxide film 9 formed on the second impurity diffusion region 7b between the first and second gate electrodes 6a and 6b are selectively removed to form a bitline contact hole 18.
As shown in FIG. 2g, a polysilicon layer is formed on the entire surface including the bitline contact hole 18 and patterned selectively to form the polysilicon pad 14 on the second impurity diffusion region 7b.
As shown in FIG. 2h, the planarizing layer 15 is formed on the entire surface of capacitor insulating film 13 and the polysilicon pad 14. A contact hole is formed through the planarizing layer 15 to expose a portion of the polysilicon pad 14. Then a polysilicon layer is deposited on the entire surface of planarizing layer 15 and in the contact hole to form the bitline 16. The bitline 16 contacts the polysilicon pad 14 through the contact hole.
The conventional DRAM and the conventional method of manufacturing the same, however, have the following problems.
First, since the bitline is formed above the storage node, the enlargement of the storage node is limited because the enlargement of the storage node may interfere with the bitline contact.
Secondly, since the oxide film is formed within the substrate by the SIMOX method, crystal defects may occur in the SOI layer formed on the oxide film during the oxygen ion implantation and heat treatment process. Thus, improvement in the yield of the wafer is limited.